Employing an extremely-thin-silicon-on-insulator (ETSOI) field effect transistor (FET) device configuration is advantageous since having such a thin channel material allows for better control over short channel effects. However, it is difficult to form passive devices, such as diodes, eFUSEs and resistors, in an ETSOI wafer due to the limited amount of silicon and topography issues.
For example, silicidation is often used in forming the passive devices in the wafer. With an extremely thin (e.g., less than 10 nanometers thick) silicon layer, it is very difficult to control the silicidation process and often the metal consumes all of the silicon, which is undesirable.
As another example, an eFUSE requires enough semiconductor material underneath and between the contacts to function properly. With an extremely thin (e.g., less than 10 nanometers thick) silicon layer, it is almost impossible to control the FUSE property, which is undesirable for autonomic chips.
Therefore, cost-effective techniques for integrating passive device fabrication with ETSOI technology would be desirable.